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256k x 16 static ram cy7c1041v33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05069 rev. ** revised september 4, 2001 041v33 features ? high speed ?t aa = 15 ns low active power ? 612 mw (max.) low cmos standby power (commercial l version) ? 1.8 mw (max.) 2.0v data retention (600 w at 2.0v retention) automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features functional description the cy7c1041v33 is a high-performance cmos static ram organized as 262,144 words by 16 bits. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1041v33 is available in a standard 44-pin 400-mil-wide body width soj and 44-pin tsop ii package with center power and ground (revolutionary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 256k x 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 1041v33 ? 2 a 9 a 10 1024 x 4096 i/o 0 ? i/o 7 oe i/o 8 ? i/o 15 ce we ble bhe top view soj 1041v33 ? 1 tsop ii we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 nc selection guide 1041v33-12 1041v33-15 1041v33-17 1041v33-20 1041v33-25 maximum access time (ns) 12 15 17 20 25 maximum operating current (ma) 190 170 160 150 130 maximum cmos standby current (ma) com ? l/ind ? l 888 8 8 com ? l l 0.5 0.5 0.5 0.5 0.5 shaded areas contain preliminary information.
cy7c1041v33 document #: 38-05069 rev. ** page 2 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v cc to relative gnd [1] .... ? 0.5v to +4.6v dc voltage applied to outputs in high z state [1] .................................... ? 0.5v to v cc + 0.5v dc input voltage [1] ................................ ? 0.5v to v cc + 0.5v current into outputs (low) ........................................ 20 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 3.3v 0.3v industrial ? 40 c to +85 c electrical characteristics over the operating range parameter description test conditions 7c1041-12v33 7c1041v33-15 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 1 +1 ? 1+1 a i oz output leakage current gnd < v out < v cc , output disabled ? 1 +1 ? 1+1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 190 170 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 40 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f=0 com ? l/ind ? l 88ma com ? ll 0.5 0.5 ma shaded areas contain preliminary information. notes: 1. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. t a is the ? instant on ? case temperature.
cy7c1041v33 document #: 38-05069 rev. ** page 3 of 11 electrical characteristics over the operating range (continued) test conditions 1041v33-17 1041v33-20 1041v33-25 parameter description min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 1+1 ? 1+1 ? 1+1 a i oz output leakage current gnd < v out < v cc , output disabled ? 1+1 ? 1+1 ? 1+1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 160 150 130 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 40 40 40 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f=0 com ? l/ind ? l8 8 8ma com ? l l 0.5 0.5 0.5 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8 pf c out i/o capacitance 8 pf note: 3. tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms 1041v33 ? 3 1041v33 ? 4 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 30 pf including jig and scope output (a) (b) 3 ns 3ns r1 317 ? 167 ? r2 351 ? venin equivalent th 1.73v
cy7c1041v33 document #: 38-05069 rev. ** page 4 of 11 switching characteristics [4] over the operating range 1041v33-12 1041v33-15 1041v33-17 parameter description min. max. min. max. min. max. unit read cycle t rc read cycle time 12 15 17 ns t aa address to data valid 12 15 17 ns t oha data hold from address change 3 33 ns t ace ce low to data valid 12 15 17 ns t doe oe low to data valid 678ns t lzoe oe low to low z 0 00 ns t hzoe oe high to high z [5, 6] 677ns t lzce ce low to low z [6] 3 33 ns t hzce ce high to high z [5, 6] 677ns t pu ce low to power-up 0 00 ns t pd ce high to power-down 12 15 17 ns t dbe byte enable to data valid 677ns t lzbe byte enable to low z 0 00 ns t hzbe byte disable to high z 678ns write cycle [7, 8] t wc write cycle time 12 15 17 ns t sce ce low to write end 10 12 12 ns t aw address set-up to write end 10 12 12 ns t ha address hold from write end 0 00 ns t sa address set-up to write start 0 00 ns t pwe we pulse width 10 12 12 ns t sd data set-up to write end 7 89 ns t hd data hold from write end 0 00 ns t lzwe we high to low z [6] 3 33 ns t hzwe we low to high z [5, 6] 678ns t bw byte enable to end of write 10 12 12 ns shaded areas contain preliminary information. notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 8. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1041v33 document #: 38-05069 rev. ** page 5 of 11 switching characteristics [4] over the operating range (continued) parameter description 1041v33-20 1041v33-25 unit min. max. min. max. read cycle t rc read cycle time 20 25 ns t aa address to data valid 20 25 ns t oha data hold from address change 3 5 ns t ace ce low to data valid 20 25 ns t doe oe low to data valid 8 10 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [5, 6] 810ns t lzce ce low to low z [6] 35ns t hzce ce high to high z [5, 6] 810ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 20 25 ns t dbe byte enable to data valid 8 10 ns t lzbe byte enable to low z 0 0 ns t hzbe byte disable to high z 8 10 ns write cycle [7,8] t wc write cycle time 20 25 ns t sce ce low to write end 13 15 ns t aw address set-up to write end 13 15 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 13 15 ns t sd data set-up to write end 9 10 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [6] 35ns t hzwe we low to high z [5, 6] 810ns t bw byte enable to end of write 13 15 ns data retention characteristics over the operating range (for l version only) parameter description conditions [10] min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 330 a t cdr [3] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns notes: 9. t r < 3 ns for the ? 12 and ? 15 speeds. t r < 5 ns for the ? 20 and slower speeds. 10. no input may exceed v cc + 0.5v.
cy7c1041v33 document #: 38-05069 rev. ** page 6 of 11 data retention waveform 1041v33 ? 5 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms notes: 11. device is continuously selected. oe , ce , bhe and/or bhe = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. read cycle no. 1 previous data valid data valid t rc t aa t oha 1041v33-6 address data out [11, 12] read cycle no. 2 (oe controlled) 1041v33-7 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble [12, 13] current i cc i sb
cy7c1041v33 document #: 38-05069 rev. ** page 7 of 11 notes: 14. data i/o is high impedance if oe or bhe and/or ble = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) write cycle no. 1 (ce controlled) 1041v33-8 t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we bhe, ble [14, 15] t write cycle no. 2 (ble or bhe controlled) t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address bhe ,ble we ce 1041v33-9
cy7c1041v33 document #: 38-05069 rev. ** page 8 of 11 truth table ce oe we ble bhe i/o 0 ? i/o 7 i/o 8 ? i/o 15 mode power h x x x x high z high z power down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) switching waveforms (continued) write cycle no.3 (we controlled , oe low) 1041v33-10 t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1041v33 document #: 38-05069 rev. ** page 9 of 11 ordering information speed (ns) ordering code package name package type operating range 12 cy7c1041v33 -12vc v34 44-lead (400-mil) molded soj commercial cy7c1041v33l-12vc v34 44-lead (400-mil) molded soj cy7c1041v33 - 12zc z44 44-pin tsop ii z44 cy7c1041v33l-12zc z44 44-pin tsop ii z44 15 cy7c1041v33 -15vc v34 44-lead (400-mil) molded soj cy7c1041v33l-15vc v34 44-lead (400-mil) molded soj cy7c1041v33 - 15zc z44 44-pin tsop ii z44 cy7c1041v33l-15zc z44 44-pin tsop ii z44 17 cy7c1041v33 - 17vc v34 44-lead (400-mil) molded soj cy7c1041v33l-17vc v34 44-lead (400-mil) molded soj cy7c1041v33 - 17zc z44 44-pin tsop ii z44 cy7c1041v33l-17zc z44 44-pin tsop ii z44 20 cy7c1041v33 - 20vc v34 44-lead (400-mil) molded soj cy7c1041v33l-20vc v34 44-lead (400-mil) molded soj cy7c1041v33 - 20zc z44 44-pin tsop ii z44 cy7c1041v33l-20zc z44 44-pin tsop ii z44 25 cy7c1041v33 - 25vc v34 44-lead (400-mil) molded soj cy7c1041v33l-25vc v34 44-lead (400-mil) molded soj cy7c1041v33 - 25zc z44 44-pin tsop ii z44 cy7c1041v33l-25zc z44 44-pin tsop ii z44
cy7c1041v33 document #: 38-05069 rev. ** page 10 of 11 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams 44-lead (400-mil) molded soj v34 51-85082-b 44-pin tsop ii z44 51-85087-a
cy7c1041v33 document #: 38-05069 rev. ** page 11 of 11 document title: cy7c1041v33 256k x 16 static ram document number: 38-05069 rev. ecn no. issue date orig. of change description of change ** 107262 09/15/01 szv change from spec number: 38-00645 to 38-05069

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